1. Field of the Invention
This invention relates to a semiconductor apparatus, and more particularly to a semiconductor apparatus including a protection device.
2. Background Art
With the recent increase in speed and capacity in the information processing technology, there has been a growing demand for frequency enhancement and downsizing on semiconductor apparatuses. In this context, MOS (metal oxide semiconductor) transistors widely used for e.g. fast switching devices or voltage converter circuits also undergo device downsizing and thinning of the gate insulating film, causing concern about the decrease of ESD (electrostatic discharge) capability. Hence there is also a rapidly growing demand for the enhancement of electrostatic breakdown capability on semiconductor apparatuses.
In a semiconductor apparatus including a MOS transistor, when the MOS transistor is formed in a silicon substrate, an ESD protection diode is often formed simultaneously. For example, in the technique disclosed in JP-A 2000-091344(Kokai), a polycrystalline silicon layer is formed on a silicon substrate. P-type layers and N-type layers are alternately arrayed in the polycrystalline silicon layer to form six stages of PN diodes connected in series in opposite direction to each other, which are connected between the gate and the source of a MOS transistor. When a surge voltage due to ESD is applied between the gate and the source of the MOS transistor, avalanche breakdown occurs in the diodes, which then become conducting, and a surge current flows through the diodes. Consequently, because the electric energy of the surge current can be consumed in the diodes, the surge voltage is prevented from being applied to the gate oxide film of the MOS transistor, and the breakdown of the gate oxide film can be prevented. This technique of forming PN diodes in the polycrystalline silicon layer is widely used because of its high flexibility in the device manufacturing process.
However, according to the inventors' investigation, it has been found that such a structure cannot sufficiently achieve the effect of the protection diode. More specifically, in the PN diode formed in the polycrystalline silicon layer, the transport of electrons or holes is greatly inhibited by electron traps or hole traps existing at the crystal grain boundary. Consequently, the mobility of these carriers in polycrystalline silicon decreases to a fraction of the mobility in single-crystal silicon. Thus the so-called snapback effect does not occur, and current increases monotonically relative to voltage. That is, there is no case where the resistance abruptly decreases and results in an increased current when the voltage exceeds a certain value, but the current increases only with the increase of voltage. Thus the operating voltage of the protection diode increases. Hence the current transport capability decreases, and the energy of the surge current cannot be sufficiently consumed. Furthermore, the amount of heat generated in the polycrystalline silicon layer upon application of ESD reaches even several 10 to 100 W. However, an oxide film is formed directly below the polycrystalline silicon layer and has an extremely high thermal resistance. Hence this protection device cannot rapidly dissipate the generated heat and is susceptible to thermal breakdown. Thus, although the above technique for forming PN diodes in the polycrystalline silicon layer is effective in simplifying the manufacturing process, its protection effect is insufficient.
To avoid such problems, PN diodes can be formed in the single-crystal silicon constituting the substrate rather than in the polycrystalline silicon layer provided on the substrate. For example, in the technique disclosed in JP-A 7-122712(Kokai) (1995), an N-type epitaxial layer is formed on an N-type silicon substrate, a P-type layer is locally formed on the surface of the N-type epitaxial layer, and a plurality of N-type regions are locally formed inside the P-type layer. Thus an NPN structure can be formed in the single-crystal silicon substrate. This NPN structure is operable as a pair of Zener diodes connected in opposite direction to each other (i.e., an NPPN structure). Alternatively, it can be regarded as the operation of an NPN transistor with the base open.
When a surge voltage is applied to this NPN structure, the resistance decreases by the snapback effect, allowing a surge current to flow. Thus a device connected in parallel to this NPN structure, such as the gate oxide film of a MOS transistor, can be protected from ESD breakdown. Furthermore, because this NPN structure is formed in the substrate, the generated heat can be dissipated through the substrate, and the thermal breakdown is less likely to occur. Thus, by forming an NPN structure in the single-crystal silicon substrate, a protection device allowing a large current flow and also being resistant to heat can be realized. However, such a protection device occupies a certain area in the substrate surface and inhibits the downsizing of the semiconductor apparatus.